Computer Architecture

ISA
Instruction Set Architecture. A high level abstraction of the hardware that implemented by a set of microprocessor design techniques.
Types like RICS: x86. CICS: MIPS, ARM

RICS
Reduced Instruction Set Computing.
Reduce the amount work of a single instruction that at most a single data memory cycle.

MISP
Microprocessor without Interlocked Pipeline Stages.
Reduce the amount of job of each instruction. Make it easier to do the pipeline to speed up.
( Use more registers. Only one memory access method, reg + offset. Return address register, use coprocessor CP0 to deal with floating points and interrupt)
TODO What does WITHOUT INTERLOCK mean?

EXcpu = Number of Instructions * CPI * cycle time

PIPELINE
Five stages: Instruction Fetch, Instruction Decode, Execution, Memory Access, Write Back.
Hazard: Structural Hazard, Data Hazard (Stall, Data Forward), Branch Hazard (Static Prediction, Dynamic Prediction)

CACHE
WHY: Balance the performance difference between CPU and memory. L1 L2 L3 cache.
The reason why cache is useful is taking advantage of temporary locality and spacial locality.
ORGANISATION: Full associate, direct mapping, two way set associate.


VIRTUAL MEMORY
WHAT: Virtual memory is a memory management technique that maps a virtual address used by program into a physical address in memory.

WHY: (1. Abstraction Layer) Each program will have a independent 4G memory space provided by the system which is a middle layer between high level software program and low level hardware memory resource. Then software program no longer needs to care about which segment of memory can be used or whether a memory is 'real' memory or disk. (2. Memory Protection) Virtual memory can help programs from interfering with others programs. Because each program can access its own memory space which maps to a part of physical memory controlled by operating system. (3. Shared Memory) Also helps programs cooperate and share memory.

HOW: Use the page table to translate virtual address to physical address and use TLB (Translation Lookaside Buffer) to accelerate the speed.

PAGE FAULT: When the hardware tries to access a page that is mapped in the virtual space however not loaded into the physical memory, then a page fault will be raised by hardware. Usually the operating system will handle page fault interrupt by allocate a new page in physical memory and map it to the demanded virtual memory.

THRASHING:
When a large process or some small processes frequently access the memory and physical memory doesn't have the enough space for these processes, and the memory swapping strategy makes inefficient  swapping decision, then pages are frequently swapped between memory and disk which costs a lot time but do less help to the program.
TODO: Cache swap replacement algorithm

OUT OF ORDER PROCESSOR
TODO: Tomasulu algorithm, register renaming, reorder buffer, reservation station, instruction window
MEMORY MODEL FOR SEQUENTIAL CONSISTENCY
TODO: Review the cs 295 content